The present invention relates to a nonvolatile semiconductor memory and particularly relates to an electrically rewritable nonvolatile semiconductor memory (EEPROM, flash memory) employing memory cells each having a stack of a floating gate (charge accumulation layer) and a control gate.
The present invention also relates to a nonvolatile semiconductor memory utilizing a multilevel storage technique.
There is conventionally known, as a nonvolatile semiconductor memory which is electrically rewritable and capable of realizing high integration, an NAND type EEPROM having a plurality of memory cells mutually connected in series.
FIG. 1A is a plan view showing one NAND cell formed on a memory cell array on an EEPROM chip and FIG. 1B is an equivalent circuit thereof. FIG. 2A is a cross-sectional view taken along the line 2Axe2x80x942A of FIG. 1A.
FIG. 2B is a cross-sectional view showing one example of a cross section taken along the line 2Bxe2x80x942B of FIG. 1A and particularly shows a case of employing an LOCOS element isolation film (312).
FIG. 3 is a cross-sectional view showing another example of a cross section taken along the line 2Bxe2x80x942B of FIG. 1A and particularly shows a case of employing a trench element isolation insulating film (322). It is noted that a portion surrounded by a dashed line corresponds to the portion shown in FIG. 2B.
As shown in FIGS. 1A, 2A, 2B and 3, a memory cell array consisting of a plurality of NAND cells are formed on a P type silicon substrate (or P type well which will be referred to as herein) 311 surrounded by the element isolation oxide film 312. One NAND cell includes, for example, eight memory cells MC (MC1 to MC8) mutually connected in series.
Each memory cell MC has a stacked gate structure. The stacked gate structure consists of an insulating film 313 formed on the P type well 311, a floating gate 314 (3141 to 3148) formed on the insulating film 313, an insulating film 315 formed on the floating gate 314 and a control gate (CG) 316 (3161 to 3168 or CG1 to CG8) formed on the insulating film 315.
An N+ diffused layer (source/drain region) 319 of one memory cell MC is shared with its adjacent memory cell MC, whereby, for example, eight memory cells MC are connected to one another in series and one NAND cell is formed.
One end of a current path of the NAND cell is connected to a bit line BL (318) through a drain-side select gate transistor ST1 and the other end thereof is connected to a source line SL through a source-side select gate transistor ST2.
The gate electrode of each of the select gate transistors ST1 and ST2 has a structure in which the floating gate 314 (3149, 31410) and the control gate 316 (3169, 31610), for example, are electrically connected with each other at a portion which is not shown.
The P type well 311, on which memory cells MC, the select gate transistors ST1, ST2 and the like are formed, is covered with a CVD oxide film 317 or the like. The bit line (BL) 318 is arranged on the CVD oxide film 317. The bit line (BL) 318 extends in column direction.
The control gate CG (CG1 to CG8) of each memory cell MC is shared among NAND cells arranged in row direction and functions as a word line WL (WL1 to WL8). The row direction is a direction orthogonal to the column direction.
The gate electrode (3149, 3169) of the drain-side select gate transistor ST1 is shared among drain-side select gate transistors ST1 arranged in row direction and functions as a drain-side select gate line SGD.
The gate electrode (31410, 31610) of the source-side select gate transistor ST2 is shared among source-side gate transistors ST2 arranged in row direction and functions as a source-side select gate line SGS.
The data stored by one memory cell MC in the NAND cell is multilevel, i.e., binary or more.
In case of storing binary data, the range of the possible threshold voltages of the memory cells MC is divided into two types which are assigned data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d, respectively. In case of the NAND type memory, the threshold voltages after data erase are normally xe2x80x9cnegativexe2x80x9d and defined as, for example, xe2x80x9c1xe2x80x9d. The threshold voltages after data write are normally xe2x80x9cpositivexe2x80x9d and defined as xe2x80x9c0xe2x80x9d.
In case of storing multilevel data, e.g., four-level data, the range of the possible threshold voltages of the memory cells MC is divided into four types, which are assigned data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d, respectively. In case the NAND type memory, the threshold voltages after data erase are normally xe2x80x9cnegativexe2x80x9d and defined as xe2x80x9c11xe2x80x9d. The threshold voltages after data write are normally xe2x80x9cpositivexe2x80x9d and defined as xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d and xe2x80x9c00xe2x80x9d in the order in which threshold voltages are higher.
It is not always necessary that only the data after data erase have xe2x80x9cnegativexe2x80x9d threshold voltages. It suffices that the range of the possible threshold voltages of memory cells MC is divided into a plurality of types. It also suffices that the polarity of a threshold voltage, i.e., whether the threshold voltage is xe2x80x9cnegativexe2x80x9d or xe2x80x9cpositivexe2x80x9d, is opposite to that described above.
In the data write operation technique of such an NAND type EEPROM, a local self boost technique (LSB technique) is recently regarded as a favorable one. The operation of the NAND type EEPROM adopting the LSB technique will be described hereinafter with reference to FIG. 1B.
Data erase is roughly divided into two ways, i.e., batch erase and block erase.
In batch erase, the data of all the memory cells MC existing on the memory cell array are simultaneously erased. In this case, the potentials of all the control gates CG (word lines WL) on the memory cell array are set at 0V, the bit lines BL and the source lines SL are turned into a floating state, respectively and then a high voltage (e.g., 20V) is applied to the P type well 311. By doing so, electrons are discharged into the P type well 311 from the floating gates 314 of all the memory cells MC existing in the memory cell array and the threshold voltages of all the memory cells MC are shifted in negative direction.
In block erase, the data of the memory cells MC existing on the memory cell array are erased in units of blocks. Normally, one block consists of a group of NAND cells which are arranged in row direction and which share control gates CG (word lines WL). In this case, the potentials of the control gates CG (word lines WL) in a select block are set at 0V, a high voltage (e.g., 20V) is applied to control gates CG (word lines WL) in non-select blocks, the bit lines BL and the source lines SL are turned into a floating state, respectively and a high voltage (e.g., 20V) is applied to the P type well 311. By doing so, electrons are discharged from the floating gates 314 of the memory cells MC existing in the select block into the P type well 31 and the threshold voltages of the memory cells MC in the select block are shifted in negative direction.
The above-stated data erase operation is executed prior to the data write operation to be conducted to the entire memory cell array or the data write operation to be conducted in block units.
Before starting the description of the data write operation, it is assumed that a select control gate CG in the select block is xe2x80x9cCG2 (word line WL2)xe2x80x9d.
In the data write operation, a predetermined positive voltage Vsgd is applied to a select gate line SGD in a select block and 0V is applied to a select gate line SGS. Also, 0V is applied to all word lines WL and all select gate lines SGD and SGS in non-select blocks.
In this state, if data write is carried out by means of the LSB technique, the select word line WL2 is applied with a high voltage Vpp for data write, non-select word lines WL1 and WL3 adjacent to the select word line WL2 are applied with 0V, respectively, and non-select word lines WL4 to WL8 other than the non-select word lines WL1 and WL3 are applied with a voltage Vpass, respectively. The voltage vpass is almost in the middle of 0V and the data write high voltage Vpp. Although 0V is applied to the non-select word lines WL1 and WL3 in the above example, a positive voltage lower than Vpass may be applied thereto.
Data write is normally carried out sequentially from the memory cell MC8 farthest from the bit line BL toward the memory cell MC1 closest thereto.
When data xe2x80x9c0xe2x80x9d (or data having a xe2x80x9cpositivexe2x80x9d threshold voltage in this example) is written, 0V (write select voltage) is applied to a select bit line BL.
The data of the memory cell MC1 closer to the bit line BL than the select memory cell MC2 is always in an erase state (which data has a xe2x80x9cnegativexe2x80x9d threshold voltage in this example). Due to this, even if the voltage of the word line WL1 is set at 0V, the voltage of 0V applied to the bit line BL is transferred to the channel of the select memory cell MC2 and to an N+ type diffused layer 319 thereof. As a result, in the select memory cell MC2, electrons move from the P type well 311 to the floating gate 314 and the threshold voltage of the select memory cell MC2 is shifted in the positive direction.
When data xe2x80x9c1xe2x80x9d (or data having a xe2x80x9cnegativexe2x80x9d threshold voltage in this example) is written, a voltage (write non-select voltage) equal to or higher than the voltage Vsgd is applied to the select bit line BL.
Here, the select gate SGD is applied with the voltage Vsgd. Due to this, the select gate transistor ST1 becomes non-conductive and the channels and N+ type diffused layers 319 of the memory cells MC1 to MC8 are turned into a xe2x80x9cfloating statexe2x80x9d, respectively. In this state, if the write high voltage Vpp and the voltage Vpass are applied to the select word line WL2 and to the non-select word lines WL4 to WL8 other than the non-select word lines WL1 and WL3, respectively, then the channel potential of the select memory cell MC2 and those of the non-select memory cells MC4 to MC8 as well as the potentials of the N+ type diffused layers 319 are increased.
The memory cells MC1 and MC3 adjacent to the select memory cell MC2 are cut off by the back-bias effect caused by the increased channel potentials. At this moment, the high voltage Vpp is applied to the control gate CG2 (word line WL2) of the select memory cell MC2. Thus, the channel potential of the select memory cell MC2 is increased further. The channel potential of the select-memory cell MC2 rises to about 8 to 9V if the high voltage Vpp is, for example, 18V and a channel boost ratio is 0.5. Namely, the potential difference between the word line WL2 and the channel of the select memory cell MC2 is decreased to a value sufficient to provide a write inhibit voltage. As a result, in the select memory cell MC2, there is little movement of electrons from the P type well 311 to the floating gate 314 and the threshold voltage of the select memory cell MC2 is kept xe2x80x9cnegativexe2x80x9d.
In data read operation, a voltage (e.g., 3.5V) for continuity is applied to the select gate lines SGD and SGS in the select block and to the control gates CG (word lines WL) of the non-select memory cells. By doing so, the select gate transistors ST1 and ST2 in the select block and the non-select memory cells are turned xe2x80x9conxe2x80x9d. In this state, a read voltage of 0V or the like is applied to the control gate CG (word line WL) of the select memory cell in the select block. At this moment, the potential of the bit line BL is changed according to a current flowing thereto through the select memory cell. Whether data is data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is determined by detecting the changed bit line potential. In case of storing four-level data, it is determined whether the data is data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d or xe2x80x9c00xe2x80x9d.
As described above, in data write operation employing the LSB technique, a voltage not less than 0V and less than Vpass is applied to non-select word lines adjacent to a select word line which is applied with a high voltage, and the voltage Vpass is applied to the remaining non-select word lines.
With such an LSB technique, it is possible to increase the channel potential of the select memory cell, thus occurrences for writing errors at the time of particularly writing data xe2x80x9c1xe2x80x9d can be suppressed. Besides, since the variation of the threshold voltages of cells becomes quite small, the LSB technique is regarded as a favorable one particularly for writing data to a multilevel memory.
Nevertheless, problems are rising in the LSB technique as cells are made smaller in size and higher integration progresses.
The greatest feature of the LSB technique is that non-select memory cells adjacent to a select memory cell must be turned into a cutoff state irrespectively of the data stored in these non-select memory cells. The non-select memory cells adjacent to the select memory cell have arbitrary threshold voltages. Owing to this, there are cases where one of the adjacent non-select memory cells has a xe2x80x9cpositivexe2x80x9d threshold voltage or both of them have xe2x80x9cnegativexe2x80x9d threshold voltages (erase state).
To cut off these adjacent non-select memory cells by means of the back-bias effect caused by the channel potential, it is necessary to sufficiently increase the voltage Vpass or to control threshold voltage distribution after data erase to thereby sufficiently increase the lowest threshold voltage.
As regard the former case, to suppress the voltage Vpass-induced variation of the threshold voltages of the non-select memory cells connected to the non-select word lines and to the selected bit line, the voltage vpass cannot be set so high. To the contrary, the lower the voltage Vpass, the more effectively the threshold voltage variation of the non-select memory cells can be suppressed and writing error can be prevented. Considering this, therefore, it is essential to set the threshold voltage distribution after data erase to be higher within the range in which the erase state can be read and to sufficiently narrow the distribution width.
It is necessary that the distribution width of the threshold voltage after erase is limited within the range of, for example, xe2x80x9cxe2x88x923V to xe2x88x920.5Vxe2x80x9d.
In these circumstances, the present applicant proposed a soft write technique. The soft write technique is to gradually write data on a memory cell after erasing data and to gradually move the threshold voltage of the memory cell in positive direction. To be specific, after data is erased, using a sufficiently low voltage as a start voltage, a write pulse is applied to word lines for each block while repeatedly stepping up the start voltage and conducting verification for each block. This makes it possible to greatly narrow the distribution width of the threshold voltages after data erase.
The write operation in an NAND type EEPROM by means of the LSB technique and a technique for controlling a threshold voltage distribution after data erase by means of the soft write technique are mentioned in detail in the following references.
Japanese Patent Application No. 10-104652 (priority application of Japanese Patent Application No. 9-124493) discloses a technique for turning a memory cell in an over-erase state to a normal state by soft write (as well as for making erase verification).
Japanese Patent Application No. 9-340971 discloses a technique for conducting soft write and erase verification after erasing data from an NAND cell, determining that there are predetermined number of memory cells which threshold voltages reach a predetermined threshold voltage to finish the soft write and turning memory cells in an over-erase state into a normal state.
Japanese Patent Application No. 9-224922 discloses a technique for conducting erase verification and over-erase detection read while erasing data from an NAND cell and conducting data erase and soft write so that the threshold voltages in an erase state can be set between a desired upper limit and a desired lower limit while monitoring the threshold voltages of the memory cells.
FIGS. 4A and 4B show the concept of the soft write technique.
As indicated by xe2x80x9cINITIALxe2x80x9d in solid line in FIG. 4B, the distribution of threshold voltages Vth after block erase or batch erase is very wide.
As indicated by xe2x80x9cTbxe2x80x9d which is gradient shown in FIG. 4A, however, a memory cell easy to erase is also easy to write.
Accordingly, by optimizing a voltage for block erase or batch erase, a start voltage for later soft write as well as a step-up width to conduct erase verification for each block, it is possible to narrow the distribution width of threshold voltages Vth after data erase as indicated by xe2x80x9cSOFTWxe2x80x9d in dotted line shown in FIG. 4B. The reason for conducting verification for each block is that it requires shorter time to complete verification than the time required for conducting verification for each bit. As a result, it is possible to narrow the distribution width of the threshold voltages Vth compared with that after block erase or batch erase. Naturally, however, the distribution width narrowed by the soft write is greatly influenced by the irregularity of the write characteristic of memory cells within the respective blocks. For that reason, there is fear that the following problems may occur to the controlling of the distribution width by means of the soft write technique as miniaturization progresses in the future.
FIG. 5A shows the dependency of write characteristic on gate length. It is noted that the dependency is obtained under constant conditions for a voltage applied during data write and for a write pulse width.
As shown in FIG. 5A, the dependency of write characteristic on gate length is particularly great when a gate length L is within the range of 0.25 xcexcm or less. This is due to the influence of process irregularity, the short channel effect and the like. The great dependency of write characteristic on gate length means that write characteristic varies according to wafers, chips and blocks as the gate length L is shorter. It is not favorable to conduct verification at the time of soft write for each bit due to the limited erase time. Verification is, therefore, conducted on a block-by-block basis.
Thus, the irregularity of write characteristic has great influence on the distribution of threshold voltages after soft write. Consequently, writing errors and the variation of the threshold voltage increase particularly in a memory cell having a gate length L decreased to not more than 0.25 xcexcm.
AS can be seen from the above, the LSB technique is a promising technique among NAND cell write techniques, for preventing writing error or threshold voltage variation which may occur during write operation.
Nevertheless, as the miniaturization of memory cells progresses, it becomes more difficult to control the distribution of threshold voltages after data erase. Such controlling is quite significant for the LSB technique. If the distribution width of threshold voltages after data erase increases, writing errors or the like occur to the write operation after erase operation, resulting in the deterioration of reliability.
In one aspect of the present invention, a method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Also, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
In another aspect of the invention, a method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. The method also includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition, the method includes setting the source potential of the memory cell to a second source potential different from the first source potential and setting the gate potential thereof to the second read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the second digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Furthermore, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a third read-out potential that is different from the first or second read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d and the bit data of the second digit is xe2x80x9c0xe2x80x9d, and determining if bit data of a third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Also, the method includes setting the source potential of the memory cell to a third source potential that is an in-between potential of the first and second source potentials and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c0xe2x80x9d and the bit data of the second digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. In addition, the method includes setting the source potential of the memory cell to the second source potential and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d and the bit data of the second digit is xe2x80x9c0xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Furthermore, the method includes setting the source potential of the memory cell to a fourth source potential that is obtained by adding the third source potential to the second source potential and setting the gate potential thereof to the third read-out potential when the bit data of the first digit is xe2x80x9c1xe2x80x9d and the bit data of the second digit is xe2x80x9c1xe2x80x9d, and determining if bit data of the third digit of the multi-bit data is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
Objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.xe2x80x9d